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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
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MITSUBISHI MICROCOMPUTERS
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M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37920S4CGP is a single-chip microcomputers designed with high-performance CMOS silicon gate technology. These are housed in 100-pin plastic molded QFP. This microcomputer supports the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of this microcomputer is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of this microcomputer enhance the memory access efficiency to execute instructions fast. This microcomputer include the 4-channel DMA controller and the DRAM controller with enhanced fast page mode. Therefore, this microcomputer are suitable for office, business, and industrial equipment controller that require fast processing of large data.
* Instruction execution time * * * * * * * * * *
The fastest instruction at 20 MHz frequency ........................ 50 ns Single power supply .................................................... 5 V 0.5 V Interrupts ........... 6 external sources, 17 internal sources, 7 levels Multi-functional 16-bit timer ................................................... 5 + 3 Serial I/O (UART or Clock synchronous) ..................................... 2 10-bit A-D converter ............................................ 4-channel inputs DMA controller .............................................................. 4-channels DRAM controller Real-time output .... 4 bits x 2 channels, or 6 bits x 1 channel + 2 bits x 1 channel 12-bit watchdog timer Programmable input/output (ports P2-P9, P12) ....................... 49
APPLICATION DISTINCTIVE FEATURES
Number of basic machine instructions .................................... 203 Memory RAM .............................................................................2048 bytes ROM ................................................................................. External Telecommunications equipment such as copiers, printers, typewriters, facsimiles, optical disk drives, HDD, mobile radio communication equipment, ISDN terminals Control devices for office automation equipment such as personal computers
* *
M37920S4CGP PIN CONFIGURATION (TOP VIEW)
A1 A2 A3 A4 A5 A6 A7 A8/MA0 A9/MA1 A10/MA2 A11/MA3 A12/MA4 A13/MA5 A14/MA6 A15/MA7 A16/MA8 A17 A18/MA9 A19 A20/MA10 A21 A22/MA11 A23 VSS MD1 D0 D1 D2 D3 D4 A0 81 P86/CLK0 82 P85/RXD0 83 P84/TXD0 84 P83/CTS0/RTS0 85 P82/CTS0/CLK1 86 P81/RXD1 87 P80/TXD1 88 VCC 89 AVCC 90 VREF 91 AVSS 92 VSS 93 P73/AN3/ADTRG/INT4 94 P72/AN2/INT3 95 P71/AN1 96 P70/AN0 97 P122/INT2/TB2IN 98 P121/INT1/TB1IN 99 P120/INT0/TB0IN 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
M37920S4CGP
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
D5 D6 D7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET NMI BYTE P30/RDY
P66/DMAREQ3 P65/TA4IN/DMAREQ2 P64/TA4OUT/DMAACK2 P63/TA3IN/DMAREQ1 P62/TA3OUT/DMAACK1 P61/TA1IN/DMAREQ0 P60/TA1OUT/DMAACK0 P57/TA2IN/RTP13 P56/TA2OUT/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P96/WRH/UCAS P95/WRL/LCAS P94/CAS/W P93/CS3/RAS3 P92/CS2/RAS2 P91/CS1/RAS1 CS0 P44/HLDA P43/HOLD P42/TC P41/1 P40/ALE P33/BHW BLW RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Outline 100P6S-A
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Write output
BLW
Data Bus (Even) Data Bus (Odd) Data Buffer DQ0 (8) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Address Bus Data Buffer DQ3 (8)
Address output circuit
Read output
RD
External data bus width select input
BYTE
Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8)
NMI
Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8)
Data I/O circuit
Reference voltage input
VREF
Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8)
Instruction register (8)
Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8)
DRAM controoler
Program Address Register PA (24)
Bus Interface Unit (BIU)
Incrementer (24)
(0 V) MD1
Incrementer/Decrementer (24) Program Counter PC (16)
(5 V) MD0
A-D converter (10)
P4(5)
Data Address Register DA (24)
Program Bank Register PG (8) Data bank Register DT (8)
Input Buffer Register IB (16)
Processor Status Register PS (11)
Watchdog timer
Timer TB2 (16)
Timer TB1 (16)
Timer TB0 (16)
Vcc
Direct Page Register DPR1 (16) Direct Page Register DPR2 (16)
Timer TA4 (16)
Timer TA3 (16)
Timer TA2 (16)
Timer TA1 (16)
Timer TA0 (16)
Reset input
P7(4)
Direct Page Register DPR0 (16)
Direct Page Register DPR3 (16)
Stack Pointer S (16) Index Register Y (16)
Clock output
BLOCK DIAGRAM
Clock Generating Circuit
Accumulator B (16) Accumulator A (16)
Clock input
Arithmetic Logic Unit (16)
2
Input/Output port P12
P12(3)
XIN
Input/Output port P9
RAM 2048 bytes
XOUT
Index Register X (16)
Central Processing Unit (CPU)
P9(7)
Input/Output port P8
RESET
P8(7)
Input/Output port P7
Input/Output port P6
UART1(9)
UART0(9)
(0 V) Vss
P6(7)
Input/Output port P5
P5(8)
Input/Output port P4
Input/Output port P3
(0 V) AVSS
P3(2)
Input/Output port P2
Instruction Queue Buffer Q7 (8)
DMA3(16) DMA2(16) DMA1(16) DMA0(16) P2(8)
AVcc
Data bus
Address bus
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
FUNCTIONS (Microcomputer mode)
Parameter Number of basic machine instructions Instruction execution time External clock input frequency f(XIN) Memory size ROM RAM Programmable input/output ports P2, P5 P3 P4 P6, P8 P7 P9 P12 Multi-functional timers TA0-TA4 TB0-TB2 Serial I/O A-D converter Watchdog timer DMA controller UART0 and UART1 Functions 203 50 ns (the fastest instruction at f(XIN) = 20 MHz) 20 MHz (Max.) External 2048 bytes 8-bit ! 2 2-bit ! 1 5-bit ! 1 7-bit ! 2 4-bit ! 1 6-bit ! 1 3-bit ! 1 16-bit ! 5 16-bit ! 3 (UART or Clock synchronous serial I/O) ! 2 10-bit successive approximation method ! 1 (4 channels) 12-bit ! 1 4 channels Maximum transfer rate 20 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 1-bus cycle transfer) 10 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 2-bus cycles transfer)
DRAM controller
1 channel Supports fast page access mode. Incorporates 8-bit refresh timer. Supports CAS before RAS refresh method or self refresh method. Chip select area ! 4 (CS0-CS3). A wait number and bus width can be set for each chip select area. 4 bits ! 2 channels; or 6 bits ! 1 channel + 2 bits ! 1 channel 6 external types, 17 internal types. Each interrupt except NMI can be set to a priority level within the range of 0-7 by software. Built-in (externally connected to a ceramic resonator or quartz crystal resonator). 5 V10 % 135 mW (at f(XIN) = 20 MHz, typ.) Input/Output withstand voltage Output current 5V 5 mA Up to 16 Mbytes. Note that bank FF16 is a reserved area. -20 to 85 C CMOS high-performance silicon gate process 100-pin plastic molded QFP
Chip-select wait control Real-time output Interrupts Clock generating circuit Power supply voltage Power dissipation Ports' input/output characteristics Memory expansion Operating temperature range Device structure Package
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Microcomputer mode)
Pin Vcc, Vss MD0 MD1 RESET XIN XOUT BYTE Name Power supply input MD0 MD1 Reset input Clock input Clock output External data bus width select input Analog power supply input Reference voltage input Low-order address Middle-order address/ DRAM address High-order address/ DRAM address Low-order data I/O port P2/ High-order data Input/ Output -- Input Input Input Input Output Input Functions Apply 5 V10 % to Vcc, and 0 V to Vss. This pin controls the processor mode. Connect this pin to VCC. Connect this pin to Vss. The microcomputer is reset when "L" level is applies to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when "L" signal is input, and 8 bits when "H" signal is input. Power supply input pin for the A-D converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter. The low-order 8 bits of address (A0-A7) are output. The middle-order 8 bits of address (A8-A15) are input/output. While DRAM space is accessed, multiplexed address (MA0-MA7) is output. The high-order 8 bits of address (A16-A23) are output. While DRAM space is accessed, multiplexed address (MA8-MA11) is output. The low-order 8 bits of data (D0-D7) are input/output. s When 8-bit external data bus is used (BYTE = "H" level) Port P2 is an 8-bit I/O port. s When 16-bit external data bus is used (BYTE = "L" level) The high-order 8 bits (D8-D15) are input/output. While the input level at pin RDY is "L", the microcomputer is placed in the ready state. While pin RD is at "L" level, the microcomputer reads out data and instruction codes. Also, pin RDY can function as a programmable I/O port pin (P30) by software. s When 8-bit external data bus is used (BYTE = "H" level) While pin BLW is at "L" level, the microcomputer writes data. s When 16-bit external data bus is used (BYTE = "L" level) While pin BLW is at "L" level, the microcomputer writes data into an evennumbered address. While pin BHW is at "L" level, the microcomputer writes data into an oddnumbered address. Signal ALE is used to latch an address. 1 has the same period as internal clock . Pin P42 functions as a programmable I/O port pin. While the input level at pin HOLD is at "L" level, the microcomputer is placed in the hold state. Signal HLDA is used to inform the external that the microcomputer enters the hold state. By software, pin ALE, clock 1 output pin, and pins HOLD, HLDA function as programmable I/O port pins (P40, P41, P43, P44). Pin P42 also functions as pin TC. Port P5 is an 8-bit I/O port. These pins also function as I/O pins for timers A0, A2, and pulse output pins for the real-time output. Port P6 is a 7-bit I/O port. These pins also function as I/O pins for timers A1, A3, A4, input pins for DMA requests, and output pins for DMA acknowledge signals.
AVcc, AVss VREF A0-A7 A8-A15/ MA0-MA7 A16-A23/ MA8-MA11 D0-D7 P20/D8- P27/D15
-- Input Output Output Output I/O I/O
P30/RDY, RD, BLW, P33/BHW
Memory control signal I/O
Input Output Output Output
P40/ALE, P41/1, P42/TC, P43/HOLD, P44/HLDA
I/O port P4
Output Output I/O Input Output
P50-P57 P60-P66
I/O port P5 I/O port P6
I/O I/O
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Pin P70-P73 I/O port P7
Name
Input/ Output I/O
Functions Port P7 is a 4-bit I/O port. P72 and P73 also function as input pins for INT3 and INT4. According to the software setting, these pins also function as input pins for the A-D converter. Port P8 is a 7-bit I/O port. These pins also function as I/O pins for UART0, UART1. This is an output pin for CS0. Port P9 is a 6-bit I/O port. According to the software setting, P91-P93 also funtion as chip select output pins. While DRAM space is selected, P94-P96 function as output pins for DRAM control signals. Port P12 is a 3-bit I/O port. These pins also functions as input pins for INT0, INT1, INT2. According to software setting, these pins also function as input pins for timers B0-B2. This pin is for a non-maskable interrupt.
P80-P86 CS0 P91-P96
I/O port P8 Chip-select output I/O port P9
I/O Output I/O
P120-P122
I/O port P12
I/O
NMI
Non-maskable interrupt
Input
5
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37920S4CGP is the same functions as the M37920F8CGP except for the following. Therefore, refer to the datasheet of the M37920F8CGP. * The M37920S4CGP does not include the internal flash memory. * The M37920S4CGP operates only in the microprocessor mode. * The M37920S4CGP does not have the flash memory control register (address 9E16). * Some of programmable I/O ports of the M37920S4CGP differ from those of the M37920FGCGP.
MEMORY
Figure 1 shows the memory map.
00000016 Bank 016 00FFFF16 01000016 Bank 116 01FFFF16 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
00000016 0000FF16 00080016
Peripheral devices control registers
Interrupt vector table 00FFC016 DMA3 DMA2 DMA1 DMA0
Address matching detect
Internal RAM 2048 bytes 000FFF16 00100016
Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1)
00FFC016 00FFFF16
INT4 INT3 A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT1 INT0 NMI Watchdog timer DBC (Note 2)
BRK instruction (Note 2)
FE000016 Bank FE16 FEFFFF16 FF000016 Bank FF16 FFFFFF16 00FFFE16
Zero divide RESET
Notes 1: Do not write to this address. 2: These are interrupts used only for debugging. Do not use these interrupts.
Fig. 1 Memory map
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation) 00000016 Reserved area (Note 1) 00000116 Reserved area (Note 1) 00000216 [Port P0 register] (Note 2) 00000316 [Port P1 register] (Note 2) 00000416 [Port P0 direction register] (Note 2) 00000516 [Port P1 direction register] (Note 2) 00000616 Port P2 register 00000716 Port P3 register 00000816 Port P2 direction register 00000916 Port P3 direction register 00000A16 Port P4 register 00000B16 Port P5 register 00000C16 Port P4 direction register 00000D16 Port P5 direction register 00000E16 Port P6 register 00000F16 Port P7 register 00001016 Port P6 direction register 00001116 Port P7 direction register 00001216 Port P8 register 00001316 Port P9 register 00001416 Port P8 direction register 00001516 Port P9 direction register 00001616 [Port P10 register] (Note 2) 00001716 [Port P11 register] (Note 2) 00001816 [Port P10 direction register] (Note 2) 00001916 [Port P11 direction register] (Note 2) 00001A16 Port P12 register 00001B16 00001C16 Port P12 direction register 00001D16 00001E16 A-D control register 0 00001F16 A-D control register 1 00002016 A-D register 0 00002116 00002216 A-D register 1 00002316 00002416 A-D register 2 00002516 00002616 A-D register 3 00002716 00002816 00002916 00002A16 00002B16 00002C16 00002D16 00002E16 00002F16 00003016 UART0 transmit/receive mode register 00003116 UART0 baud rate register (BRG0) 00003216 UART0 transmit buffer register 00003316 00003416 UART0 transmit/receive control register 0 00003516 UART0 transmit/receive control register 1 00003616 UART0 receive buffer register 00003716 00003816 UART1 transmit/receive mode register 00003916 UART1 baud rate register (BRG1) 00003A16 UART1 transmit buffer register 00003B16 00003C16 UART1 transmit/receive control register 0 00003D16 UART1 transmit/receive control register 1 00003E16 UART1 receive buffer register 00003F16
Address (Hexadecimal notation) 00004016 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C16 00004D16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C16 00005D16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C16 00006D16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C16 00007D16 00007E16 00007F16 Count start register One-shot start register Up-down register Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Particular function select register 2 Reserved area (Note 1) Debug control register 0 Debug control register 1 Address comparison register 0
Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register
Notes 1: Do not read/write to this address. 2: These registers are used in the bus fixation of the power saving function. For details, refer to the section on the power saving function of the M37920F8CGP datasheet.
Fig. 2 Location of peripheral devices' control registers (1)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation) 00008016 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C16 00008D16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C16 00009D16 00009E16 00009F16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA16 0000AB16 0000AC16 0000AD16 0000AE16 0000AF16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA16 0000BB16 0000BC16 0000BD16 0000BE16 0000BF16 CS0 control register L CS0 control register H CS1 control register L CS1 control register H CS2 control register L CS2 control register H CS3 control register L CS3 control register H
Address (Hexadecimal notation) 0000C016 0000C116 0000C216 0000C316 0000C416 0000C516 0000C616 0000C716 0000C816 0000C916 0000CA16 0000CB16 0000CC16 0000CD16 0000CE16 0000CF16 0000D016 0000D116 0000D216 0000D316 0000D416 0000D516 0000D616 0000D716 0000D816 0000D916 0000DA16 0000DB16 0000DC16 0000DD16 0000DE16 0000DF16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA16 0000EB16 0000EC16 0000ED16 0000EE16 0000EF16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA16 0000FB16 0000FC16 0000FD16 0000FE16 0000FF16 Source address register 0 L Source address register 0 M Source address register 0 H Destination address register 0 L Destination address register 0 M Destination address register 0 H Transfer counter register 0 L Transfer counter register 0 M Transfer counter register 0 H DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 L Source address register 1 M Source address register 1 H Destination address register 1 L Destination address register 1 M Destination address register 1 H Transfer counter register 1 L Transfer counter register 1 M Transfer counter register 1 H DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 L Source address register 2 M Source address register 2 H Destination address register 2 L Destination address register 2 M Destination address register 2 H Transfer counter register 2 L Transfer counter register 2 M Transfer counter register 2 H DMA2 mode register L DMA2 mode register H DMA2 control register Source address register 3 L Source address register 3 M Source address register 3 H Destination address register 3 L Destination address register 3 M Destination address register 3 H Transfer counter register 3 L Transfer counter register 3 M Transfer counter register 3 H DMA3 mode register L DMA3 mode register H DMA3 control register
Area CS0 start address register Area CS1 start address register Area CS2 start address register Area CS3 start address register
Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Real-time output control register Pulse output data register 0 Pulse output data register 1 Reserved area (Note 1) DRAM control register Refresh timer
CTS/RTS separate select register
DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register
Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1)
Note 1: Do not read/write to this address.
Fig. 3 Location of peripheral devices' control registers (2)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Processor mode
The M37920S4CGP operates only in the microprocessor mode exclusive for the external ROM. Be sure to fix the level at pin MD0 to Vcc and the level at pin MD1 to Vss. Also, be sure to fix bits 1, 0 at address 5E16 (the processor mode register 0) to "1" and "0", respectively.
Table 1. Relationship between pins MD0, MD1 and processor mode Pin MD0 VCC level (5 V) Pin MD1 VSS level (5 V) Processor mode After reset, the microcomputer starts its operation in the microprocessor mode. (Be sure to pin MD0 to Vcc level.)
Microprocessor mode
When the microcomputer starts its operation after reset with the level at pin MD0 = Vcc level (5 V), the microcomputer is placed in the microprocessor mode.
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0 Processor mode register 0 Processor mode bits 0 0 : Do not select. 0 1 : Do not select. 1 0 : Microprocessor mode 1 1 : Do not select.
Address 5E16
External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : Do not select. Software reset bit By a write of "1" to this bit, the microcomputer will be reset, and then, restarted. Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as a programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as the clock 1 output pin.)
Fig. 4 Processor mode register 0's bit configuration
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
0
0
0
Processor mode register 1 Fix this bit to "0". Direct page register switch bit 0 : Only DPR0 is used. 1 : DPR0 to DPR3 are used.
Address 5F16
RDY input select bit 0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.) 1 : RDY input is enabled. (P30 functions as pin RDY.) ALE output select bit 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area. HOLD input, HLDA output select bit 0 : HOLD input and HLDA output are disabled. (P40 and P44 function as programmable I/O port pins.) 1 : HOLD input and HLDA output are enabled. (P43 and P44 function as pins HOLD and HLDA, respectively.) "0" at read.
Fig. 5 Processor mode register 1's bit configuration
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Port P9 direction register Port P10 direction register Port P11 direction register Port P12 direction register A-D control register 0 A-D control register 1 UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register UART 0 Transmit/Receive control register 0 UART 1 Transmit/Receive control register 0 UART 0 Transmit/Receive control register 1 UART 1 Transmit/Receive control register 1 Count start register One-shot start register Up-down register Timer A clock division select register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register (0416)*** (0516)*** (0816)*** (0916)*** (0C16)*** (0D16)*** (1016)*** (1116)*** (1416)*** (1516)*** (1816)*** (1916)*** (1C16)*** 0016 0016 0016 0000 00000 0016 0000000 0000 0000000 0000000 0016 0016 000 Processor mode register 0 Processor mode register 1 Watchdog timer Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Debug control register 0 Debug control register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART 0 transmit interrupt control register UART 0 receive interrupt control register UART 1 transmit interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Processor status register PS Program bank register PG Program counter PCH Program counter PCL Direct page registers DPR0 to DPR3 Data bank register DT Stack pointer
Address (5E16)*** (Note 2) 0 0 0 1 0 (5F16)*** 0 0 (6016)*** (6116)*** (6216)*** (6316)*** (6616)*** 1 (6716)*** 0 0 0 (6E16)*** (6F16)*** (7016)*** (7116)*** (7216)*** (7316)*** (7416)*** (7516)*** (7616)*** (7716)*** (7816)*** (7916)*** (7A16)*** (7B16)*** (7C16)*** (7D16)*** (7E16)*** (7F16)***
(Note 2)
(Note 2)
0
00
FFF16 0 00 0 0 (Note 3)
(Note 3)
(Note 3)
000
(Note 3)
0000 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000
(1E16)*** 0 0 0 0 0 ? ? ? (1F16)*** (3016)*** (3816)*** 0000001 0016 0016
(3416)*** 0 0 0 0 1 0 0 0 (3C16)*** 0 0 0 0 1 0 0 0 (3516)*** 0 0 0 0 0 0 1 0 (3D16)*** 0 0 0 0 0 0 1 0 (4016)*** (4216)*** 0 0016 00000
(4416)*** 0 0 0 0 0 0 0 0 (4516)*** (5616)*** (5716)*** (5816)*** (5916)*** (5A16)*** (5B16)*** 0 0 ? (5C16)*** 0 0 ? (5D16)*** 0 0 ? 0016 0016 0016 0016 0016 0000 0000 0000 00
000??0001?? 0016 Contents at address FFFF16 Contents at address FFFE16 000016 0016 FFF16
Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: At power-on reset, these bits are clear to "0". At hardware or software reset, on the other hand, these bits retain the state just before reset.
Fig. 6 Microcomputer internal status just after reset (1)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Address CS0 control register L CS0 control register H CS1 control register L CS1 control register H CS2 control register L CS2 control register H CS3 control register L CS3 control register H Area CS0 start address register Area CS1 start address register Area CS2 start address register Area CS3 start address register Real-time output control register
DRAM control register
Address
(Note 2)
(8016)*** (8116)***
10
0
(Note 3)
10
DMA0 interrupt control register DMA1 interrupt control register DMA2 interrupt control register DMA3 interrupt control register DMA0 mode register L DMA0 mode register H DMA0 control register DMA1 mode register L DMA1 mode register H DMA1 control register DMA2 mode register L DMA2 mode register H DMA2 control register DMA3 mode register L DMA3 mode register H DMA3 control register
(B216)*** (B316)*** (B416)*** (B516)***
0000 0000 0000 0000
001
(Note 3)
(8216)*** 0 1 0 0 0 (8316)*** 0 (8416)*** 0 1 0 0 0 (8516)*** 0 (8616)*** 0 1 0 0 0 (8716)***
10
000
(Note 3)
10
(CC16)*** 0 0 0 0 0 0 0 0 (CD16)*** 0 0 0 0 0 0 0 0 (CE16)*** 0 0 0 0 0 0 0 0 (DC16)*** 0 0 0 0 0 0 0 0 (DD16)*** 0 0 0 0 0 0 0 0 (DE16)*** 0 0 0 0 0 0 0 0 (EC16)*** 0 0 0 0 0 0 0 0 (ED16)*** 0 0 0 0 0 0 0 0 (EE16)*** 0 0 0 0 0 0 0 0 (FC16)*** 0 0 0 0 0 0 0 0 (FD16)*** 0 0 0 0 0 0 0 0 (FE16)*** 0 0 0 0 0 0 0 0
000
(Note 3)
10
000
(8A16)*** 0 0 0 1 0 0 0 0 (8C16)*** 0 0 0 0 0 0 0 0 (8E16)*** 0 0 0 0 0 0 0 0 (9016)*** 0 0 0 0 0 0 0 0 (A016)*** 0 0 0 0 0 0 0 0 (A816)*** 0 0 0 0 0 0 0 0 (AC16)*** 0 0 0 0 0 0 0 0 (B016)*** 0 0 0 0 0 0 0 0 (B116)*** 0 0 0 0 0 0 0 0
CTS/RTS separate select register DMAC control register L DMAC control register H
Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: While Vss level voltage is applied to pin BYTE, these bits are "0". While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are "1".
Fig. 7 Microcomputer internal registers' status just after reset (2)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
INPUT/OUTPUT PINS
Each of ports P3 to P9 and P12 has an direction register, and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is "1", and an input pin when it is "0". When a pin is programmed as an output pin, the data written to its port latch is output to the output pin. When a pin is programmed as an output pin, the contents of the port latch are read out instead of the value of the pin. Accordingly, a previously output value can be read out correctly even when the output "H" voltage is lowered or the output "L" voltage is raised, owing to an external load, etc. A pin programmed as an input pin is placed in the flooting state, and the value input to the pin can be read out correctly. When a pin is programmed as an input pin, the data can be written only in the port latch, and the pin remains floating. Each of Figures 8 and 9 shows the block diagram for each port pin.
Table 2. Correspondence between external buses, bus control signals, and programmable I/O port pins
External buses, Bus control signals A0 to A7, A8 to A15, A16 to A23 D0 to D7, D8 to D15 RD, BLW, BHW CS0
Standby state select bit 0 A0 to A7, A8 to A15, A16 to A23 1 P100 to P107 (Note 2), P110 to P117 (Note 2), P00 to P07 (Note 2)
D0 to D7, P10 to P17 (Note 2), D8 to D15 (Note 1) P20 to P27 RD, BLW, BHW (Note 1) CS0 P31, P32 (Note 2), P33 P90 (Note 2)
Notes 1: When the external data bus width = 8 bits (BYTE = VCC level), this becomes a programmable I/O port pin, regardless of the standby state select bit's contents. 2: Pin functions of port pins P0, P1, P31, P32, P90, P10, P11 are not shown in the pin configuration. However, relationship with corresponding bus signals and ports is listed in Table 2. For the addresses of these port's registers and direction registers, refer to the location of the perpheral devices' control registers (Figures 2 and 3).
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
[Inside dotted-line not included] P20/D8 to P27/D15, P33/BHW [Inside dotted-line included] P30/RDY, P43/HOLD, P61/TA1IN/DMAREQ0, P63/TA3IN/DMAREQ1, P65/TA4IN/DMAREQ2, P66/DMAREQ3, P81/RxD1, P85/RxD0, P120/INT0/TB0IN, P121/INT1/TB1IN, P122/INT2/TB2IN
Direction register
Data bus
Port latch
Direction register
P40/ALE, P41/1, P44/HLDA, P60/TA1OUT/DMAACK0, P62/TA3OUT/DMAACK1, P64/TA4OUT/DMAACK2, P80/TxD1, P84/TxD0, P91/CS1/RAS1, P92/CS2/RAS2, P93/CS3/RAS3, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS
"1"
Output (Internal peripheral devices)
Data bus
Port latch
[Inside dotted-line not included] P52/RTP02, P53/RTP03, P54/RTP10, P55/RTP11 [Inside dotted-line included] P51/TA0IN/RTP01, P57/TA2IN/RTP13
Data bus
Direction register
Port latch
Latch
Timer underflow signal
T CK
Q
P50/TA0OUT/RTP00, P56/TA2OUT/RTP12
Direction register "1"
Output (Internal peripheral devices)
Data bus
Port latch
Latch Timer underflow signal
T CK
Q
Fig. 8 Block diagram for each port pin (1)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
[Inside dotted-line not included] P70/AN0, P71/AN1 [Inside dotted-line included] P72/AN2/INT3, P73/AN3/ADTRG/INT4
Direction register
Data bus
Port latch
Analog input
P82/CTS0/CLK1, P83/CTS0/RTS0, P86/CLK0
"1" "0" Direction register
Output (Internal peripheral devices)
Data bus
Port latch
P42/TC
Direction register "0"
Output (TC)
Data bus
Port latch
RD, BLW, CS0, A0 to A23, D0 to D7
Direction register "1"
Output (Internal peripheral devices)
Data bus
Port latch
Fig. 9 Block diagram for each port pin (2)
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC AVCC VI Parameter Power source voltage Analog power source voltage Input voltage D0-D7, D8/P20-D15/P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, VREF, XIN, RESET, BYTE, MD0, MD1, NMI Output voltage A0-A23, RD, BLW, BHW/P33, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, XOUT Power dissipation Operating temperature Storage temerature Ratings -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V V
VO
-0.3 to VCC+0.3 300 -20 to 85 -40 to 150
V mW C C
Pd Topr Tstg
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = -20 to 85 C, unless otherwise noted)
Limits Symbol VCC AVCC VSS AVSS VIH Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage Parameter Min. 4.5 Typ. 5 VCC 0 0 Max. 5.5 Unit V V V V V
VIH VIL
High-level input voltage Low-level input voltage
VIL IOH (peak)
Low-level input voltage High-level peak output current
IOH (avg)
High-level average output current
IOL (peak)
Low-level peak output current
IOL (avg)
Low-level average output current
P20-P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI D0-D7, D8-D15 P20-P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI D0-D7, D8-D15 A0-A23, RD, BLW, BHW/P33, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122 A0-A23, RD, BLW, BHW/P33, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122 A0-A23, RD, BLW, BHW/P33, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122 A0-A23, RD, BLW, BHW/P33, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122
0.8VCC
VCC
0.5VCC 0
VCC 0.2VCC
V V
0
0.16VCC -10
V mA
-5
mA
10
mA
5
mA
f(XIN)
External clock input frequency
20
MHz
Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for A0-A23, D0-D7, D8/P20-D15/P27, ports P80-P86 must be 80 mA or less, the sum of IOH(peak) for A0-A23, D0-D7, D8/P20-D15/P27, ports P80-P86 must be 80 mA or less, the sum of IOL(peak) for ports P30, RD, BLW, BHW/P33, CS0, P40-P44, P50-P57, P60-P66, P70-P73, P91-P96, P120-P122 must be 80 mA or less, the sum of IOH(peak) for P30, RD, BLW, BHW/P33, CS0, P40-P44, P50-P57, P60-P66, P70-P73, P91-P96, P120-P122 must be 80 mA or less.
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted)
Symbol VOH Parameter High-level output voltage A0-A23, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P93, P120-P122 High-level output voltage A0-A23, CS0, D0-D7, D8/P20-D15/P27, P40, P44, P91-P93 High-level output voltage RD, BLW, BHW/P33, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Low-level output voltage A0-A23, CS0, D0-D7, D8/P20-D15/P27, P30, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P93, P120-P122 Low-level output voltage A0-A23, CS0, D0-D7, D8/P20-D15/P27, P40, P44, P91-P93 Low-level output voltage RD, BLW, BHW/P33, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Hysteresis TA0IN-TA4IN, TB0IN-TB2IN, INT0-INT4, DMAREQ0-DMAREQ3, ADTRG, CTS0, CLK0, CLK1, NMI, RDY, HOLD, RxD0, RxD1 Hysteresis RESET Hysteresis XIN High-level input current D0-D7, D8/P20-D15/P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input current D0-D7, D8/P20-D15/P27, P30, P33, P40-P44, P50-P57, P60-P66, P70-P73, P80-P86, P91-P96, P120-P122, XIN, RESET, BYTE, MD0, MD1, NMI RAM hold voltage Power source current Test conditions IOH = -10 mA Min. 3 Limits Typ. Max. Unit V
VOH
IOH = -400 A
4.7
V
VOH
IOH = -10 mA IOH = -400 A IOL = 10 mA
3.4 4.8 2
V
VOL
V
VOL
IOL = 2 mA
0.45
V
VOL
IOL = 10 mA IOL = 2 mA 0.4
1.6 V 0.4 1 V
VT+ --VT-
VT+ --VT- VT+ --VT- IIH
0.5 0.1 VI = 5.0 V
1.5 0.3 5
V V A
IIL
VI = 0 V
-5
A
VRAM ICC
When clock is stoped. At reset in micro- f(XIN) = 20 MHz. processor mode, output-only pins Ta = 25 C when are open, and the clock is stopped. other pins are con- Ta = 80 C when nected to Vss. clock is stopped.
2 25 50 1 20
V mA A
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V 10 %, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---------- ---------- RLADDER tCONV VREF VIA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage VREF = VCC VREF = VCC VREF = VCC f(XIN) 20 MHz 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5 5.9 2.45 (Note) 2.7 0 Test conditions Limits Min. Max. 10 3 2 Unit Bits LSB LSB k
s
VCC VREF V V
Note: This is applied when A-D conversion freguency (AD) = f1().
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz unless otherwise noted) For limits depending on f(XIN), their calculation formulas are shown below. Also, the values at f(XIN) = 20 MHz are shown in ( ).
Timer A input (Count input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 40 40 Max. Unit ns ns ns
Timer A input (Gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(XIN) 20 MHz f(XIN) 20 MHz f(XIN) 20 MHz Limits Min. 16 x 109 (800) f(XIN) 9 8 x 10 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns
Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz.
Timer A input (External trigger input in one-shot pulse mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter f(XIN) 20 MHz Limits Min. 8 x 109 f(XIN) 80 80 (400) Max. Unit ns ns ns
Timer A input (External trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Limits Min. 80 80 Max. Unit ns ns
Timer A input (Up-down input and Count input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Timer A input (Two-phase pulse input in event counter mode)
Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time Parameter Limits Min. 800 200 200 Max. Unit ns ns ns
*Gating input in timer mode *Count input in event counter mode *External trigger input in one-shot pulse mode *External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL)
*Up-down input and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input)
tw(UPL)
TAiOUT input (Up-down input) TAiIN input (When count at falling) TAiIN input (When count at rising)
th(TIN-UP)
tsu(UP-TIN)
*Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) TAjOUT input tsu(TAjOUT-TAjIN) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Timer B input
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
(Count input in event counter mode) Parameter Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns
TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count)
Timer B input
Symbol tc(TB) tw(TBH) tw(TBL)
(Pulse period measurement mode) Parameter Limits Min. 16 x 10 9 (800) f(XIN) 8 x 109 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns
TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width
f(XIN) 20 MHz f(XIN) 20 MHz f(XIN) 20 MHz
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz.
Timer B input
Symbol tc(TB) tw(TBH) tw(TBL)
(Pulse width measurement mode) Parameter Limits Min. 16 x 10 9 (800) f(XIN) 8 x 109 (400) f(XIN) 9 8 x 10 (400) f(XIN) Max. Unit ns ns ns
TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width
f(XIN) 20 MHz f(XIN) 20 MHz f(XIN) 20 MHz
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) 20 MHz.
A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width Limits Min. 1000 125 Max. Unit ns ns
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MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Parameter Limits Min. 200 100 100 0 20 90 Max. Unit ns ns ns ns ns ns ns
80
External interrupt (INTi) input, NMI input
Symbol tw(INH) tw(INL) Parameter INTi input/NMI input high-level pulse width INTi input/NMI input low-level pulse width Limits Min. 250 250 Max. Unit ns ns
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) RxDi input tw(INL) INTi input NMI input tsu(D-C) th(C-D)
tw(INH)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
23
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING
Timing requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD) RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Parameter Limits Min. 40 40 0 0 Max. Unit ns ns ns ns
Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Limits Symbol Parameter Min. Max. td(1-HLDAL) HLDA output delay time 20 td(RDH-HLDAL) HLDA low-level output delay time after read tc -15 (Note) td(BXWH-HLDAL) HLDA low-level output delay time after write tc -15 (Note) tpxz(HLDAL-RDZ) Floating start delay time 10 -15 tpxz(HLDAL-BXWZ) Floating start delay time 10 -15 tpxz(HLDAL-CSiZ) Floating start delay time 10 -15 tpxz(HLDAL-ALEZ) Floating start delay time 10 -15 tpxz(HLDAL-AZ) Floating start delay time 10 -15 tpzx(HLDAL-RDZ) Floating release delay time 0 tpzx(HLDAL-BXWZ) Floating release delay time 0 tpzx(HLDAL-CSiZ) Floating release delay time 0 tpzx(HLDAL-ALEZ) Floating release delay time 0 tpzx(HLDAL-AZ) Floating release delay time 0
Note: tc = 1/f(XIN).
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
24
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
RDY input
1
RD BLW BHW
tsu(RDY-1)
RDY input
th(1-RDY)
: Wait inserted by software (The above is applied when 1 wait is selected.) : Wait inserted by Ready function
HOLD input
1
tsu(HOLD-1)
HOLD input
th(1-HOLD)
td(1-HLDAL)
HLDA output
td(1-HLDAL)
td(RDH-HLDAL)
tpxz(HLDAL-RDZ)
Hi-Z
tpzx(HLDAL-RDZ)
RD
td(BXWH-HLDAL)
BLW BHW
tpxz(HLDAL-BXWZ)
Hi-Z
tpzx(HLDAL-BXWZ)
tpxz(HLDAL-CSiZ)
CSi
Hi-Z
tpzx(HLDAL-CSiZ)
tpxz(HLDAL-ALEZ)
ALE
Hi-Z
tpzx(HLDAL-ALEZ)
tpxz(HLDAL-AZ)
A0-A23 output
Hi-Z
tpzx(HLDAL-AZ)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V *HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
25
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
External bus timing
For limits depending on f(XIN), their calculation formulas are shown below. W = 0 (0 wait) W = 1 (1 wait) W = 2 (2 wait) tc = 1/f(XIN).
Timing Requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tc tw(half) tw(H) tw(L) tr tf ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) Parameter External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Limits When 0/1/2 wait is selected When ALE expansion wait is selected Unit Min. 50 0.45tc 0.5tc - 8 0.5tc - 8 Max. 0.55tc Min. 50 0.45tc 0.5tc - 8 0.5tc - 8 Max. 0.55tc ns ns ns ns ns ns ns ns ns ns ns ns ns
8 8 (2 + W)tc - 45 (1.5 + W)tc - 35 (1 + W)tc - 30 15 0 (1 + W)tc - 35 0 0 15 0
8 8 4tc - 45 3.5tc - 35 2tc - 30
2tc - 35
External clock input
tw(L)
f(XIN)
tw(H)
tr
tf
tc tw(half)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) *Input timing voltage : 2.5 V (tc, tw(half))
26
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Limits Symbol td(1-RDL) td(1-RDH) td(1-BXWL) td(1-BXWH) tw(ALEH) td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Parameter Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time ALE pulse width ALE completion delay time after address stabilization Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read Address hold time after read (Note 3) ALE completion delay time after read start Read disable valid time after ALE completion Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write Address hold time after write (Note 3) ALE completion delay time after write start Write disable valid time after ALE completion Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write Floating start delay time after write When 0/1/2 wait is selected When ALE expansion wait is selected Unit Min. -10 -10 -10 -10 0.5tc - 20 tc - 30 (1 + W)tc - 15 tc - 15 tc - 15 tc - 30 8 20 0.5tc - 20 (1.5 + W)tc - 20 0.5tc - 20 tc - 15 (1 + W)tc - 15 tc - 15 tc - 15 tc - 30 8 20 0.5tc - 20 (1.5 + W)tc - 20 0.5tc - 20 (1 + W)tc - 20 0.5tc - 10 0.5tc + 10 0.5tc - 20 1.5tc - 20 3.5tc - 20 0.5tc - 20 2tc - 20 0.5tc - 10 0.5tc + 10 0.5tc - 20 1.5tc - 20 3.5tc - 20 0.5tc - 20 tc - 15 2tc - 15 2tc - 15 tc - 15 2tc-30 8 Max. 15 10 15 10 Min. -10 -10 -10 -10 tc - 20 1.5tc - 30 2tc - 15 2tc - 15 tc - 15 2tc - 30 8 Max. 15 10 15 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). However, except for the case at instruction prefetch.
27
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Normal access: 0/1/2 wait
tc
f(XIN)

1
Bus cycle
td(1-RDL) tw(ALEH)
ALE
td(1-RDH)
td(A-ALEL) tw(RDH)
tw(RDL)
RD
td(RDH-ALEL)
BLW BHW
td(RDH-BXWH)
td(A-RDH)
A0-A23
th(RDH-A)
td(CSiL-RDH) td(CSiL-RDL)
CSi
th(RDH-CSiL)
ta(A-D) ta(CSiL-D) ta(RDL-D)
D0-D7, D8-D15
td(RDH-D) tsu(D-RDL) th(RDH-D)

1
Bus cycle
td(1-BXWL) tw(ALEH)
ALE
td(1-BXWH)
td(A-ALEL)
RD
td(BXWH-RDH)
tw(BXWH)
BLW BHW
tw(BXWL)
td(A-BXWH)
A0-A23
td(BXWH-ALEL)
th(BXWH-A)
td(CSiL-BXWH) td(CSiL-BXWL)
CSi
th(BXWH-CSiL)
td(D-BXWL)
D0-D7, D8-D15
th(BXWH-D)
tpxz(BXWH-DZ)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi)
28
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
Normal access : ALE extension wait
tc
f(XIN)

1
Bus cycle
tw(ALEH)
ALE
td(1-RDL) td(ALEL-RDH)
td(1-RDH)
td(A-ALEL) tw(RDH)
tw(RDL)
RD
td(RDH-BXWH)
BLW BHW
td(A-RDH)
A0-A23
th(RDH-A)
td(CSiL-RDH)
CSi
td(CSiL-RDL)
th(RDH-CSiL)
ta(A-D) ta(CSiL-D) ta(RDL-D)
D0-D7, D8-D15
td(RDH-D) tsu(D-RDL) th(RDH-D)

1
Bus cycle
tw(ALEH)
ALE
td(1-BXWL) td(ALEL-BXWH)
td(1-BXWH)
td(A-ALEL) td(BXWH-RDH)
RD
tw(BXWH)
BLW BHW
tw(BXWL)
td(A-BXWH)
A0-A23
th(BXWH-A)
td(CSiL-BXWH)
CSi
td(CSiL-BXWL)
th(BXWH-CSiL)
td(D-BXWL)
D0-D7, D8-D15
th(BXWH-D)
tpxz(BXWH-DZ)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi)
29
PR
30
Burst ROM access : 0/1/2 wait at instruction prefetch
MI ELI
tw(ALEH)
Y NAR
ALE
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
tw(RDH)
td(RDH-ALEL)
RD
td(A-ALEL) td(RDH-BXWH)
BLW BHW
td(A-RDH)
th(RDH-A)
A0-A23
td(CSiL-RDH)
th(RDH-CSiL)
CSi
ta(A-D) ta(BA-D) ta(BA-D)
ta(BA-D)
ta(CSiL-D) th(BA-D) th(BA-D) th(BA-D) th(RDH-D)
ta(RDL-D)
D0-D7, D8-D15
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
M37920S4CGP
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi)
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DRAM access
Timing Requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol ta(RASL-D) ta(CASL-D) th(CASH-D) RAS access time CAS access time Data input hold time after CAS Parameter Limits Min. Max. 2.5tc - 35 tc - 30 Unit ns ns ns
0
Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(RASH) td(CASH-RASH) th(RASL-CASH) th(CASL-RASL) tw(CASL) td(RA-RASH) th(RASL-RA) td(CA-CASH) th(CASH-CA) td(WH-CASH) td(WL-CASH) th(CASL-WL) td(D-CASH) th(CASL-D) tpxz(CASH-D) td(CAF-CASH) td(WFL-CASH) td(DF-CASH) tpxz(WH-D) Parameter Min. RAS high-level pulse width CAS high-level valid time before RAS CAS high-level hold time after RAS's low level RAS hold time after CAS's low level CAS low-level pulse width Row address valid time before RAS Row address hold time after RAS's low level Column address valid time before CAS Column address hold time after CAS's high level W high-level valid time before CAS W low-level valid time before CAS W hold time after CAS's low level Data output valid time before CAS Data output hold time after CAS's low level Floating start delay time after CAS Column address valid time before CAS (When fast page access ON is selected) W low-level valid time before CAS (When fast page access ON is selected) Data output valid time before CAS (When fast page access ON is selected) Floating start delay time after write 1.5tc - 20 1.5tc - 20 1.5tc - 20 tc - 15 tc - 15 0.5tc - 25 tc - 40 0.5tc - 20 0 3tc - 15 tc - 15 tc - 15 tc - 20 1.5tc - 15 0.5tc + 10 tc - 40 0.5tc - 20 0.5tc - 20 0.5tc + 10 Limits Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
31
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DRAM access : fast page access = OFF
1
tw(RASH)
RASi
th(RASL-CASH) td(CASH-RASH)
LCAS,UCAS (CAS)
th(CASL-RASL) tw(CASL)
td(RA-RASH)
A0-A23 Row address
td(CA-CASH) th(CASH-CA)
Column address Row address
Column address
th(RASL-RA) td(WH-CASH)
W (WRL,WRH)
ta(RASL-D) ta(CASL-D) th(CASH-D)
D0-D7, D8-D15
tw(RASH)
RASi
th(RASL-CASH) td(CASH-RASH)
LCAS,UCAS (CAS)
th(CASL-RASL) tw(CASL)
td(RA-RASH)
A0-A23 Row address
td(CA-CASH)
Column address
th(CASH-CA)
Row address
Column address
th(RASL-RA) td(WL-CASH)
W (WRL,WRH)
th(CASL-WL)
td(D-CASH)
D0-D7, D8-D15
th(CASL-D)
tpxz(CASH-D) Test conditions *Vcc = 5 V 10 %, Ta = 0 to 70 C *Input timing voltage : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi)
32
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DRAM access : fast page access = ON
1
RASi th(CASL-RASL) td(CASH-RASH)
LCAS,UCAS (CAS)
tw(RASH)
th(RASL-CASH)
tw(CASL)
tw(CASL)
tw(CASL)
td(RA-RASH) A0-A23
td(CA-CASH)
Row address
th(CASH-CA)
Column address
td(CAF-CASH)
th(CASH-CA)
Column address
td(CAF-CASH)
th(CASH-CA)
Column address
th(RASL-RA) td(WH-CASH) W (WRL,WRH) ta(RASL-D) ta(CASL-D) D0-D7, D8-D15 th(CASH-D) ta(CASL-D) th(CASH-D) ta(CASL-D) th(CASH-D)
RASi th(CASL-RASL) td(CASH-RASH) LCAS,UCAS (CAS) td(RA-RASH) A0-A23 td(CA-CASH)
Row address
tw(RASH)
th(RASL-CASH)
tw(CASL)
tw(CASL)
tw(CASL)
th(CASH-CA)
Column address
td(CAF-CASH)
th(CASH-CA)
td(CAF-CASH)
th(CASH-CA)
Column address
Column address
th(RASL-RA) td(WL-CASH) W (WRL,WRH) td(D-CASH) D0-D7, D8-D15 tpxz(WH-D) Test conditions *Vcc = 5 V 10 %, Ta = 0 to 70 C *Input timing voltage : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi) th(CASL-D) td(DF-CASH) th(CASL-D) td(DF-CASH) th(CASL-D) th(CASL-WL) td(WFL-CASH) th(CASL-WL) td(WFL-CASH) th(CASL-WL)
33
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DRAM refresh
Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = 0 to 70 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(RASCBRL) tw(CASCBRL) td(CASCBRL-RASCBRH) td(RASCBRL-CASCBRL) td(CASSLFRL-RASSLFRH) th(RASSLFRH-CASSLFRL) Parameter RAS low-level pulse width (At CAS before RAS refresh) CAS low-level pulse width (At CAS before RAS refresh) RAS high-level valid time after CAS's low level start (At CAS before RAS refresh) CAS low-level valid time after RAS's low level start (At CAS before RAS refresh) RAS high-level valid time after CAS's low level start (At self refresh) CAS low-level hold time after RAS's high level (At self refresh) Limits Min. 2tc - 15 2tc - 15 tc - 15 tc - 15 tc - 15 -15 Max. Unit ns ns ns ns ns ns
15
34
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DRAM refresh : CAS before RAS refresh
1
tw(RASCBRL)
RASi
td(CASCBRL-RASCBRH)
td(RASCBRL-CASCBRL)
tw(CASCBRL)
LCAS,UCAS (CAS)
W (WRL,WRH)
Refresh cycle
DRAM refresh : self refresh
1
RASi
td(CASSLFRL-RASSLFRH)
LCAS,UCAS (CAS)
th(RASSLFRH-CASSLFRL)
W (WRL,WRH)
Refresh cycle
Test conditions *Vcc = 5 V 10 %, Ta = 0 to 70 C *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi) *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi)
35
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
MI ELI
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
DMA transfer timing
Timing Requirements (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tsu(TCINL-1) tw(TCINL) tsu(DRQL-1) tw(DRQL) TC input setup time TC input pulse width DMAREQi input setup time DMAREQi input pulse width Parameter Limits Min. 40 tc + 20 40 tc Max. Unit ns ns ns ns
Switching characteristics (VCC = 5 V 10 %, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 20 MHz, unless otherwise noted) Symbol tw(TCL) td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Parameter TC output pulse width TC output start delay time after read TC output start delay time after write DMAACK low-level output valid time after TC output start Limits Min. tc - 20 tc - 15 tc - 15 2.5tc - 20 Max. Unit ns ns ns ns
3 k
TC 50 pF
Test circuit for TC output
36
PR
e. n. atio chang cific o spe bject t l fina su ot a its are is n m This etric li m ice: Not e para Som
I LIM E
Y NAR
MITSUBISHI MICROCOMPUTERS
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
qTC input
1
tsu(TCINL-1) tw(TCINL)
TC input
qDMAREQi input
1
tsu(DRQL-1) tw(DRQL)
DMAREQi input
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
qTransfer terminate timing
Final tranfer cycle Terminate processing (Next bus cycle)
ALE
RD BLW BHW
A0-A23
CSi
D0-D7, D8-D15
tw(TCL)
TC
td(RDH-TCL) td(BXWH-TCL)
DMAACKi
td(TCL-DMAACKL)
Test conditions *Vcc = 5 V 10 %, Ta = -20 to 85 C *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
37
P
. nge tion ifica t to cha pec al s subjec fin re a ot a is n limits his e: T ametric ic Not e par Som
IM REL
I
Y NAR
MITSUBISHI MICROCOMPUTERS
.
M37920S4CGP
16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
100P6S-A
EIAJ Package Code QFP100-P-1420-0.65 HD D
100 1 81 80
Plastic 100pin 14!20mm body QFP
JEDEC Code - Weight(g) 1.58 Lead Material Alloy 42
e
MD
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.1 - 0 10 0.35 - - - - 1.3 14.6 - - - - 20.6
HE E
30
51
31
50
A
L1
A2
b
A1
e y
F
Detail F
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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(c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Sep. 1999. Specifications subject to change without notice.
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REVISION DESCRIPTION LIST
Rev. No. 1.00 First Edition Revision Description
M37920S4CGP Datasheet
Rev. date 990916
(1/1)

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